1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a synchronous semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device, such as dynamic random access memories (DRAMs), often adopts multiple-bank architecture. The multiple-bank architecture allows virtually eliminating the RAS precharge time (often referred to as tRP) by alternately or sequentially activating multiple banks, and thereby effectively reduces the access time and cycle time. One recent trend is the increase in the number of banks within a semiconductor memory device for achieving the increased memory capacity and improved random access performance; the number of banks within a DRAM is typically increased up to eight or more. Another recent trend is the increase in the bit width within a semiconductor memory device, which is accompanied by the increase in the number of internal data buses. These two trends are undesirably accompanied by the increase in the chip size.
Japanese Patent Gazette No. 3,252,895 discloses semiconductor memory device architecture for avoiding the increase in the chip size due to the increase in the number of banks. In the disclosed semiconductor memory device architecture, data transmission lines are commonly used among different banks. FIG. 1A illustrates the structure of the disclosed semiconductor memory device, and FIG. 1B illustrates a detailed circuit structure of the disclosed semiconductor memory device.
Referring to FIG. 1A, the disclosed semiconductor memory device includes a pair of banks A and B in which a plurality of sub-arrays SAR are arranged in rows and columns. Sense amplifiers SA and a sub-word driver SWD are provided for each of the sub-arrays SAR in each of the banks. Referring to FIG. 1B, memory cells Cell (one shown) are arranged at intersections of sub-word lines SWL and bit lines BL and /BL. The sub-word lines extend in the X direction from the sub-word driver SWD, and the bit lines BL and /BL extends in the Y direction from the sense amplifiers SA.
The disclosed semiconductor memory device has a hierarchical I/O line structure. Specifically, a pair of local I/O lines LIO are provided along the X direction for every a number of sub-arrays SAR within each of the banks. Each pair of the local lines LIO are connected to an equalizer circuit LIOEQ. Referring back to FIG. 1A, pairs of global I/O lines GIO are provided along the Y direction. The global I/O lines GIO are commonly used between the banks A and B. Each pair of the global I/O lines GIO are connected to an equalizer circuit GIOEQ and an input/output amplifier DA/WA.
FIG. 1B illustrates a structure of each sub-array SAR. The local I/O lines LIO are connected to the global I/O lines GIO through I/O bridge switches 231 (one shown). The connections between the local I/O lines LIO and the global I/O lines GIO are controlled by SWIO control circuits 230 (one shown). The SWIO control circuits 230 are each composed of an AND circuit having a first input connected to a mat select signal line RACT_ik and a second input connected to an I/O switch line IOSW_k. A mat select signal line RACT_ik is provided for each “mat” within each bank; it should be noted that a “mat” designates one row of the sub-arrays SAR. The suffix “i” indicates the associated mat, and the suffix “k” indicates the associated bank. The mat select signal lines RACT_ik extend along the X direction. On the other hand, each IO switch line IOSW is provided for multiple columns of sub-arrays SAR. The IO switch lines IOSW_k extend along the Y direction. In response to the activation of the associated mat select signal lines RACT_ik and I/O switch lines IOSW_k, the SWIO control circuits 230 turn on the associated I/O bridge switches 231 to provide connections between the local I/O lines LIO and the global I/O lines GIO.
Additionally, bit lines BL and /BL are connected with the local I/O lines through column select switches 232 (one shown). The connections between bit lines BL and /BL and the local I/O lines LIO are controlled by column selection signal lines YSW (one shown) as shown in FIG. 1B. The column selection signal lines YSW extend from Y decoders YDEC in the Y direction. One column selection signal line YSW is provided for each column of the memory cells Cell.
In order to provide timing control of the mat select signal lines RACT_ik, the IO switch lines IOSW_k, the column selection signal lines YSW, and so forth, the semiconductor memory device further includes a timing control circuit (row/column timing control circuit) 100 and a command decoder 300, as shown in FIG. 2. The command decoder 300 decodes signals received from I/O pins to generate commands corresponding thereto. Such command scheme is one of the features of a synchronous semiconductor memory device, such as a SDRAM (synchronous DRAM). For example, the command decoder 300 outputs an ACTcmd signal indicative of an issue of an ACT command, a PREcmd signal indicative of an issue of a PRE command, and a RWcmd signal indicative of an issue of a READ or WRITE command. It should be noted that the ACT command indicates to activate a selected bank, a PRE command indicates to perform pre-charge operation for a selected bank, and READ and WRITE commands indicate to implement read and write operations, respectively.
The timing control circuit 100 is responsive to the commands received from the command decoder 300 to output a set of timing signals to desired signal lines and circuits. For example, the timing control circuit 100 provides mat select timing signal RACTS_A and RACTS_B to the banks A and B, respectively, to indicate the activation timing of the mat select signal lines RACT_iA and RACT_iB, it should be noted that the mat select signal lines RACT_iA and RACT_iB are collectively denoted by the symbol “RACT_ik” in FIG. 1B. The mat select timing signals RACTS_A and RACTS_B are indicative of whether the banks A and B are placed into a “row active state”, respectively; it should be noted that the row active state designates a state in which the row address for the next access is already given to a certain bank, and the bank is waiting for a read or write operation.
In addition, the timing control circuit 100 develops column activation signal RWS_A and RWS_B, which is indicative of the activation of the selected columns of the sub-arrays SAR. The column activate signal RWS_A and RWS_B are used for developing IO switch I/O switch timing signals SWIO_A and SWIO_B on the respective IO switch lines IOSW_A and IOSW_B; it should be noted that the IO switch lines IOSW_A and IOSW_B are collectively denoted by the symbol “IOSW_k” in FIG. 1B. The I/O switch timing signals SWIO_A and SWIO_B are used to control timings when the connections between the global I/O lines GIO and the local I/O lines LIO are established. Referring to FIG. 1B, the SWIO control circuits 230 are responsive to the mat select timing signal RACTS_k and the I/O switch timing signals SWIO_k for establish the connections between the global I/O lines GIO and the local I/O lines LIO.
Moreover, the timing control circuit 100 develops column select timing signals YSWS_A and YSWS_B, which are indicative of the activation timing of the column selection signal lines YSW. In response to the activation of the column select timing signal YSWS_A or YSWS_B, a selected column select line YSW is activated, and the local I/O lines LIO are connected with the selected bit lines BL and /BL. The column select timing signals YSWS_A and YSWS_B are indicative of the timings at which the associated columns of the memory cells are activated. Moreover, the timing control circuit 100 outputs a GIO equalization timing signal /EQ to the equalizer circuits GIOEQ at desired timing. This allows each global IO line pairs to be equalized to the same potential.
In this semiconductor memory device, “data refreshing” of a selected sub-array SAR is performed as follows. In response to an issue of an ACT command, the mat select timing signal RACTS_k (RACTS_A or RACTS_B) is activated to select the bank and mat associated with the selected sub-array SAR. This is followed by activating the associated main word line and sub-word lines SWL, and this results in that cell data stored on the memory cells associated with the selected sub-word line SWL is transferred to the associated bit lines BL and /BL. Each sense amplifier amplifies the voltage between the associated bit lines BL and /BL to identify the cell data, and the identified cell data are restored onto the associated memory cells Cell. The same goes for all the associated sub-word lines SWL. This is followed by an issue of a PRE command. In response to the PRE command, the relevant mat select timing signal RACTS_k is deactivated, and the main word line and the sub-word line SWL associated therewith are deactivated. After the memory cells are disconnected from the bit lines BL and /BL, the sense amplifiers SA are deactivated and the bit lines BL and /BL are equalized. This completes the data refreshing operation.
Data write operation into a selected memory cell within a selected sub-array SAR is performed as follows. In response to an issue of an ACT command, the mat select timing signal RACTS_k associated with the selected bank is activated, and the bank and mat associated with the selected sub-array SAR is selected and activated. In response to an issue of an RW command, write data is then transferred to the global I/O lines GIO via the input/output amplifier DA/WA. Desired one of the I/O switch timing signals SWIO_k is then activated in response the activation of the associated column activation signal RWS_k, and the local I/O lines LIO associated with the selected sub-array SAR is connected to the global I/O lines GIO. This is followed by connecting the bit lines BL and /BL associated with the selected memory cell with the associated local I/O lines LIO in response to the activation of the column select timing signal YSWS_k. As a result, the data on the global GIO is written into the selected memory cell through the local I/O lines LIO and the bit lines BL and /BL.
Data read operation from a selected memory cell within a selected sub-array SAR is performed as follows. In response to an issue of an ACT command, desired one of the mat select timing signals RACTS_A and RACTS_B is activated to select the bank and mat associated with the selected sub-array SAR. This is followed by activating the column activation signal RWS_k in response to an issue of an RW command, the desired IO switch timing signal SWIO_k is activated on the desired IO switch line IOSW_k. This results in that the local I/O lines LIO associated with the selected sub-array SAR is connected to the global I/O lines GIO. This is followed by connecting the bit lines BL and /BL associated with the selected memory cell with the local I/O lines LIO in response to the activation of the associated column select timing signal YSWS_k. As a result, the data stored in the selected memory cell is read to the local I/O lines LIO through the bit lines BL and /BL, and is transferred to the input/output amplifier DA/WA via the global I/O lines GIO.
FIG. 3 is a block diagram showing a structure of the conventional timing control circuit 100. The timing control circuit 100 receives an internal clock ICLK through a delay circuit 210. The timing of the received internal clock ICLK is adjusted by the delay circuit 210 so as to satisfy timing requirements, such as setup and hold times with respect to input data, including bank addresses. The conventional timing control circuit 100 includes first to fourth logic circuits 110, 120, 130, and 140.
The first logic circuit 110 generates the GIO equalization timing signal /EQ. Specifically, the first logic circuit 110 includes an AND gate 111, a delay circuit 112, and a buffer 113. The AND gate 111 receives the internal clock ICLK and the RWcmd signal on the inputs thereof, and outputs the results of the logical AND operation to the delay circuit 112. The output signal of the AND gate 111 is transferred to the equalizer circuits GIOEQ through the delay circuit 112 and the buffer 113, and used as the GIO equalization timing signal /EQ. Here, the delay time of the GIO equalization timing signal /EQ is adjusted to “tD1” by the delay circuit 112. The equalizer circuits GIOEQ are required to equalize the global I/O lines GIO, while none of the column selection signal lines YSW are not selected, and also to stop equalizing the global I/O lines GIO so as not to corrupt data on the GIO when the desired column select signal line YSW is selected. The delay time tD1 of the GIO equalization timing signal /EQ is adjusted to satisfy such timing requirements.
The second logic circuit 120 generates the column select timing signals YSWS_A and YSWS_B; it should be noted that FIG. 3 only illustrates the circuitry associated with one of the column select timing signals YSWS_A and YSWS_B, and the symbol “YSWS_k” collectively denotes the column select timing signals YSWS_A and YSWS_B. The second logic circuit 120 includes an AND gate 121, a delay circuit 122, and a buffer 123 for each of the column select timing signals YSWS_A and YSWS_B. The AND gate 121 receive the internal clock ICLK, the RWcmd signal, and a bank address selection signal ADD_BA indicative of the selection of the associated bank address, and outputs the result of the logic operation to the delay circuit 122. The output signal of the AND gate 121 is transferred to Y decoders YDEC through the delay circuit 122 and the buffer 123, and used as the column select timing signal YSWS_k. Here, the delay time of the column select timing signal YSWS_k is adjusted to “tD2” by the delay circuit 122. The Y decoders (YDEC) receive the column select timing signal YSWS_k and a column address signal ADD_COL for identifying the selected memory cell, to activate the corresponding column select signal line YSW. The delay time tD2 of the timing signal YSWS_k is adjusted so as to satisfy timing skew requirements with respect to the column address signal ADD_COL.
The third logic circuit 130 generates the column activation signals RWS_A and RWS_B; it should be noted that FIG. 3 only illustrates the circuitry associated with one of the column activation signal RWS_A and RWS_B, and the symbol “RWS_k” collectively denotes the column activation signal RWS_A and RWS_B. The third logic circuit 130 includes an AND gate 131, a D-flipflop 132, a delay circuit 133, and a buffer 134 for each of the column activation signal RWS_A and RWS_B. The AND gate 131 receives the RWcmd signal and the bank address selection signal ADD_BA, and outputs the result of the logic operation to the D-flipflop 132. The D-flipflop 132 latches the output of the AND gate 131 upon the pull-up of the internal clock ICLK to the “High” level (or upon the rising edge). The output signal of the D-flipflop 132 is outputted through the delay circuit 133 and the buffer 134, and used as the column activation signal RSW_k. The column activation signal RSW_k is transferred to buffers developing the I/O switch timing signals SWIO_k within each bank. The I/O switch timing signals SWIO_k are fed to the SWIO control circuits 230. Here, the delay time of the column activation signal RSW_k is adjusted to “tD3” by the delay circuit 133. The delay time tD3 is adjusted so as to switch the I/O switch timing signals SWO_k while none of the column select signal lines YSW is selected.
The fourth logic circuit 140 generates the mat select timing signal RACTS_A and RACTS_B; it should be noted that FIG. 3 only illustrates the circuitry associated with one of the mat select timing signal RACTS_A and RACTS_B, and the symbol “RACTS_k” collectively denotes the mat select timing signal RACTS_A and RACTS_B. The fourth logic circuit 140 includes a pair of AND gates 141 and 142, an SR flipflop 143, a delay circuit 144, and a buffer 145 for each of the mat select timing signal RACTS_A and RACTS_B. The AND gate 141 receives the ACTcmd signal, the internal clock ICLK, and the bank address selection signal ADD_BA, and outputs the result of the logic operation to the S input of the SR flipflop 143. The AND gate 142 receives the PREcmd signal, the internal clock ICLK, and the bank address selection signal ADD_BA, and outputs the result of the logic operation to the R input of the SR flipflop 143. The SR flipflop 143 is set by the output of the AND gate 141, and reset by the output of the AND gate 142. The output signal of the flip-flop 143 is outputted through the delay circuit 144 and the buffer 145, and used as the mat select timing signal RACTS_k. The mat select timing signal RACTS_k is fed to a mat selector circuit 220 associated therewith. Here, the delay time of the mat select timing signal RACTS_k is adjusted to “tDR” by the delay circuit 144. The mat selector circuit 220 receives the mat select timing signal RACTS_k and row address signals ADD_ROW to select the mat select signal lines RACT_ik. The delay time tDR of the mat select timing signal RACTS_k is adjusted so as to satisfy timing skew requirements with respect to the row address signals ADD_ROW.
FIG. 4 is a timing chart showing an exemplary operation of the conventional semiconductor memory device. In this operation, the burst length is set to four. The duration of the cycle of the internal clock ICLK is referred to as the symbol “tCK”, and the duty ratio of the internal clock ICLK is set to 50%. Read operations of the banks A and B are alternately implemented.
Initially, the bank A is deactivated with the mat select timing signal RACTS_A set to the “low” level, and the bank BANK_B is activated with the mat select timing signal RACTS_B set to the “High” level.
The read operation of the bank A begins with an issue of an ACT_A command that indicates the timing control circuit 100 to activate the bank A. The ACT_A command is latched at a time T0. The fourth logic circuit 140 activates the mat select signal RACTS_A (that is, pulls up the mat select signal RACTS_A to the “High” level), after a lapse of the delay time tDR(Rise) from the time T0.
At a time T1 within the next clock cycle, a read command R1_B is issued for the bank B. In response to the read command R1_B, the first logic circuit 110 deactivates the GIO equalization timing signal /EQ after a lapse of the delay time tD1, and the second and third logic circuits 120 and 130 activate the column select timing signal YSWS_B and the IO switch timing signal SWIO_B, after a lapse of the respective delay times tD2, and tD3 from the time T1, respectively. In response to the deactivation of the GIO equalization timing signal /EQ (that is, the pull-up of the timing signal /EQ to the “high” level), the equalization of the global I/O lines GIO is stopped. In addition, in response to the activation of the timing signals SWIO_B and YSWS_B, the global I/O lines GIO are connected to the local I/O lines LIO associated with the selected mat within the bank B (which are denoted by LIO_B, hereinafter), and the local I/O lines LIO_B are connected to the bit lines BL and /BL. Consequently, the data read by the sense amplifier SA_B associated with the selected memory cell is transferred to the global I/O lines GIO via the local I/O lines LIO within the bank BANK_B. It should be noted that the data transfer is performed during the next clock cycle of the clock cycle when the read command R1_B for the bank BANK_B is issued.
After the data transfer is completed, the GIO equalization timing signal /EQ is activated to equalize the global I/O lines GIO, and the column select timing signal YSWS_B is deactivated to disconnect he selected bit lines BL and /BL from the local I/O lines LIO_B. The IO switch timing signal SWIO_B is then deactivated to disconnect the local I/O lines LIO_B from the global I/O lines GIO.
At a time T2 within the next clock cycle, a read command R1_A is issued for the bank A. In response to the read command R1_A, the GIO equalization timing signal /EQ is deactivated after a lapse of the time tD1 from the time T2, and the column select timing signal YSWS_A and the IO switch timing signal SWIO_A. are activated and set to the “High” level. In response to the activation of the column select timing signal YSWS_A and the IO switch timing signal SWIO_A, the global I/O lines GIO are connected to the local I/O lines LIO associated with the selected mat within the bank A (referred to as the local I/O lines LIO_A), and also the selected local I/O lines LIO_A are connected to the selected bit lines BL and /BL. Consequently, the data read by the sense amplifier SA_A associated with the selected bit lines BL and /BL is transferred to the global I/O lines GIO via the local I/O lines LIO_A.
After the data transfer is completed, the GIO equalization timing signal /EQ is activated to equalize the global I/O lines GIO, and the column select timing signal YSWS_A is deactivated to disconnect the selected bit lines BL and /BL from the local I/O lines LIO_A. The IO switch timing signal SWIO_B is then deactivated to disconnect the local I/O lines LIO_A from the global I/O lines GI.
Subsequently, a read command R1′_B is issued for the bank B at a time T3 within the next clock cycle, and a read command R1′_A is then issued for the bank A at a time T4 within the following clock cycle. It should be noted that the read command R1′_A for the bank A indicates to initiate a burst read operation of the bank A. In response to the successive issues of the read command R1′_B, and read command R1′_A, the I/O switch timing signals SWIO_B and SWIO_A are successively activated after lapses of the delay time tD3 from the times T3 and time T4, respectively, to establish connections of the relevant local I/O lines within the banks A and B with the global I/O lines GIO. Consequently, the read operation of the bank B is performed, and then the first burst cycle of the burst read operation of the bank A is performed.
At a time T5 within the next clock cycle, a PRE_B command is issued to indicate the deactivation of the bank B. After a lapse of the delay time tDR(fall) from the time T5, the mat select signal RACTS_B is pulled down to the “Low” level to deactivate the bank B.
During this clock cycle, the second burst cycle of the burst read operation of the bank A is performed. Here, the IO switch timing signal SWIO_A remains activated from the previous clock cycle, and the connections between the global I/O lines GIO and the selected local I/O lines LIO_A are maintained.
Subsequently, the third and fourth burst cycles are performed with respect to the bank A at times T6 and T7, respectively. Here, the I/O switch timing signal SWIO_A also remains activated and the connections between the global I/O lines GIO and the selected local I/O lines LIO_A are maintained. At a time T8, the PRE_A command is issued to indicate the deactivation of the bank A, and the bank A is then deactivated after a lapse of the delay time tDR(Fall) from the time T8.
In order to implement the above stated operations, the delay times tD1 to tD3 are configured so as to satisfy requirements described below. Firstly, it is necessary to stop the equalization of the global I/O lines GIO so as not to corrupt the data thereon, when any of the column select signal lines YSW is activated. To satisfy this requirement, the delay time tD1 of the GIO equalization timing signal /EQ is determined as being equal to the delay time tD2 of the column select timing signals YSWS_A and YSWS_B.
Additionally, in order to prevent the global I/O lines GIO from being affected by noise due to the switching of the I/O switch timing signals SWIO_A and SWIO_B, the I/O switch timing signals SWIO_A and SWIO_B are switched while none of the column select signal lines YSW is activated. More specifically, the delay time tD3 of the I/O switch timing signals SWIO_A and SWIO_B (or of the column activation signals RSW_A and RWS_B) is set so as to satisfy the following equation:tD1−½tCK<tD3+α<tD1,  (1)where α denotes a delay time within the SWIO control circuits 230. From this equation (1), the following equations can be obtained, which express a margin t1 between the activation timings of the I/O switch signals SWIO_A and SWIO_B and the column select timing signals YSWS_A and YSWS_B, and a margin t2 between the deactivation timings of the I/O switch signals SWIO_A and SWIO_B and the column select timing signals YSWS_A and YSWS_B:t1=tD1−(tD3+α) , and  (2)t2=(tD3+α)−(tD1−½tCK)  (3)
As shown above, the conventional semiconductor memory device architecture allows the data transfer I/O lines to be commonly used among the different banks. Also, in order to eliminate the influence of noise on the global I/O lines GIO, the I/O switch timing signal SWIO_k associated with the selected bank is activated during the “column access” to the target bank. In other words, the I/O switch timing signal SWIO_k is activated or deactivated in synchronization with column cycles or CAS cycles.
One drawback of the above-described operation is the increase in the operating current due to frequent switching of the I/O switch timing signals SWIO_A and SWIO_B. The I/O switch timing signals SWIO_A and SWIO_B are turned on/off in a cycle of column selection (hereinafter referred to as “column cycle”), when read operations of the banks A and B are alternately performed. This undesirably increases the operating current of the memory device. The increase in the operating current is enhanced due to the recent increase in the number of IO switch lines IOSW from the requirement for wide bit width configuration. Thus, there is a need for providing a technique for reducing the operating current of the semiconductor memory device.
There is also a need for providing a sufficient timing margin to thereby stabilize the high-speed (or high-frequency) operations. In order to reduce noise influence resulting from switching of the I/O switch timing signals SWIO_A and SWIO_B, it is necessary to sufficiently provide the margin t1 expressed by equation (2). The margin t1, however, could not be provided even by setting the delay time tD3 to zero, when the delay time tD1 is further shortened with advances in circuit and processing technologies. This would interfere with the implementation of high-speed and high-frequency operations. Therefore, it is desired to provide a technology for improving the stability in high-speed (or high-frequency) operations.
As for the margin t2 expressed by equation (3), no noise effect will be caused by switching the I/O switch timing signals SWIO_A and SWIO_B, because the operations of the data amplifier is completed before the column select timing signal YSWS_A and YSWS_B are deactivated. The semiconductor memory device is operable even with the margin t2 less than 0 by sufficiently providing a margin between the time when the I/O switch timing signal SWIO_A and SWIO_B are switched and the time when the operation of the data amplifier is completed. In general, no problem will occur even with the margin t2 set to zero.
The following is descriptions of other related arts. Firstly, Japanese Laid Open Patent Application No. JP-A-Heisei 9-73776 discloses a synchronous semiconductor memory device that includes data terminals used for external data input/output, and memory arrays associated with the respective data terminals. Each memory array is divided into a plurality of banks operating independently from one another, which are aligned in the direction of the memory cell rows. The banks within each memory array are respectively provided with global I/O buses, and the global IO buses are electrically connected to the same data terminal.
Japanese Laid Open Patent Application No. Jp-A 2000-11639 discloses a semiconductor memory device in which a memory cell array is divided into a plurality of banks arranged in the word line direction of the memory cell array. Each of the banks is further divided into a plurality of sub-blocks arranged in the word line direction. The corresponding sub-blocks within the respective banks are addressed by the same column address. Access to memory cells selected by the address is implemented for each of the sub-blocks. The activation of the sub-blocks is carried out by a control circuit provided for the sub-blocks, on the basis of signals activated in response to the address signal for each of the banks and sub-blocks.
Japanese Laid Open Patent Application No. Jp-A 2000-173269 discloses a semiconductor memory device that includes a plurality of memory cell blocks arranged in the bit line direction, a plurality of local data line pairs (LIOs), a global data line pair (GIO), a plurality of read gate amplifiers, and a current supply load circuit. The local data line pairs LIOs are associated with the plurality of memory blocks, and each of the local data line pairs LIO is electrically connected with the associated memory block. The global data line pair GIO is commonly used among the plurality of memory blocks. The read gate amplifiers are provided between the associated local data line pairs LIO and the global data line pair GIO, and the current supply load circuit is connected with the global data line pair GIO. Here, the read gate amplifiers are designed to transfer signals from the associated local data lines LIO to the global data line GIO with the local data lines LIO and the global data line GIO disconnected electrically. In addition, the current supply load circuit is design to develop currents of same magnitude on the data lines of the global data line pair.
Japanese Laid Open Patent Application No. JP-A 2003-346497 discloses a semiconductor memory device that includes a row address latch circuit for latching an externally-provided row address input in synchronization with a timing signal, a column address latch circuit for latching a column address input from outside in synchronization with the timing signal, a command decoder, and a row address pre-latch circuit. The command decoder, upon an issue of a command requesting the semiconductor memory device to be placed into the test mode, generates a test mode signal for a predetermined period. In addition, when other commands are issued which request the semiconductor memory device to be placed into the normal operation mode, the command decoder generates command signals associated with the issued commands. The row address pre-latch circuit holds a row address except for a bank address input together with a pre-charge command, and outputs the row address to the row address latch circuit.
Japanese Laid Open Patent Application No. 2000-67577 discloses a synchronous semiconductor memory device in which the distribution methods of the internal clock signal are changeable in accordance with system operation modes. When placed into a single data rate SDRAM operation mode, the synchronous semiconductor memory device operates an input/output buffer circuit in synchronous with an external clock signal. When place into a double data rate SDRAM operation mode, on the other hand, the synchronous semiconductor memory device generates an internal clock signal having a frequency twice of the external clock signal, and operates the input/output buffer circuit in synchronous with the internal clock signal.